FPGA core developer Slamy began work on the Philips CD-i core for the MiSTer FPGA some time ago. Earlier today, an update was released. A compiled version of the core is available on the MiSTer FPGA Discord server, and a Patreon post provides detailed information about the update and how Dragon’s Lair is now performing.
Key Points
Work on the MPEG decoder for MiSTer FPGA has shown progress.
A video recording demonstrates the MiSTer core starting Dragon’s Lair and playing the intro.
Some video artifacts are present, but performance is impressive overall.
MPEG decoding is not fully in Verilog; it uses the pl_mpeg library.
The pl_mpeg library was modified to use hardware acceleration.
Video decoding is handled by 3 RISC-V soft cores:
- 1 core manages MPEG bitstream decoding.
- 2 cores handle number crunching.
The RISC-V cores are based on VexiiRiscv, achieving nearly 1 cycle per instruction.
These RISC-V cores are clocked at 80 MHz, running well on the Cyclone V (DE10 Nano).
MPEG audio decoding is simpler, handled by 1 VexiiRiscv core at 30 MHz.
The FPGA is currently about half full with this setup.
This demonstrates that a Philips CD-i with DVC on MiSTer FPGA is achievable.
Grab the WIP Philips CD-i Core here. Join the MiSTer Discord server for access, click here for an invite.
well thats super cool, cant wait to try it on my superstation
Hopefully it’ll even more further along by then.